1. Field of the Disclosure
The present disclosure generally relates to memory systems and, more particularly, to a system and method to repair memory addresses without enable fuses.
2. Brief Description of Related Art
FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 14 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 14 may constitute memory address pins or address bus 17, data pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 20. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 20 generally arranged in rows and columns to store data in rows and columns as discussed hereinbelow with reference to FIGS. 2A-2B. Each memory cell 20 may store a bit of data. A row decode circuit 22 and a column decode circuit 24 may select the rows and columns in the memory cells 20 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 20 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) unit 26. The I/O unit 26 may include a number of data output buffers (not shown) to receive the data bits from the memory cells 20 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O unit 26 may further include a clock synchronization unit or delay locked loop (DLL) 28 to synchronize the external system clock (e.g., the clock used by the memory controller (not shown) to clock address, data and control signals between the memory chip 12 and the controller) with the internal clock used by the memory 12 to perform data write/read operations on the memory cells 20.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, etc. The memory chip 12 communicates with other devices connected thereto via the pins 14 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
The memory chip 12 may also include a plurality of fuse banks 25 wherein each fuse bank may be activated when its corresponding enable fuse is blown as discussed later hereinbelow. A fuse bank allows selection of a redundant memory location when a non-redundant or actual memory location corresponding to an address stored in the fuse bank is defective. For example, a state of the art DRAM (Dynamic Random Access Memory) device may have anywhere from 128 Megabits (1024×1024×128) to 1 Gigabits (1024×1024×1024) or more of data storage. Each memory bit is made up of a storage cell capacitor and an access device transistor. With such large numbers of bits, there is nearly a 100% chance that any one memory device or chip will have multiple defective bits. To compensate for these defects, redundant bits or redundant memory cells are manufactured into the memory array to logically replace defective bits. For every 1024 rows, there may be two or four additional redundant rows, and for every 1024 columns, there may be four or eight additional redundant columns.
FIGS. 2A-2B depict exemplary sets of memory cells 29, 32 and associated fuse bank arrays 30-31, 33-34. As shown in FIGS. 2A-2B, the memory cells (e.g., the memory cells 20 in FIG. 1) may include a non-redundant or “actual” memory array containing rows R0-R7 and columns C0-C7, and corresponding redundant or “backup” memory containing rows RR0-RR3 and columns RC0-RC3. Each cell in the memory array may be identified by its corresponding row and column address. In the memory cells 29 and 32, there are 12×12=144 memory cells, which include “actual” and “redundant” memory locations. As noted before, the small number of redundant memory cells are also provided on the chip 12 to prevent data storage errors in case of the presence of any defective bits or cells in the non-redundant memory locations defined by rows R0-R7 and columns C0-C7 in the illustrations in FIGS. 2A and 2B.
Typically, separate redundant memory arrays are not used. Rather, redundant rows (RR) and redundant columns (RC) are added to the main array (e.g., the array defined by rows R0-R7 and columns C0-C7 in FIGS. 2A, 2B). In the configuration of FIG. 2A, for example, if there are one or more defective cells or bad bits in the fifth row (R4) at columns C0 and C2, then these bad bits may be repaired by using redundant row-1 (RR1) instead of “regular” row R4 as shown in FIG. 2A. As another example, FIG. 2B illustrates that a bad bit at R1-C5 is repaired by using redundant column-3 (RC3). In this case, row-1 (R1) will still be used during data transfer, but when column-5 (C5) is addressed (for any row), the redundant column RC3 will be used instead of C5. The selection and activation of a redundant row/column is typically performed using a corresponding fuse bank as discussed below.
It is also possible to repair bad redundant bits. For example, if RR1 has a bad bit at C2, one of the redundant columns can be used to repair it (e.g., column RC0). In this case, RR1 may be used in place of R4 (as shown in FIG. 2A), and RC0 may be used in place of C2 (in a manner similar to that illustrated and discussed with reference to FIG. 2B). Therefore, typically, single defective memory locations are not repaired by selecting the row and column of that bad location, but rather by replacing an entire row or column of memory elements with a redundant row or column.
Each redundant row and column requires nonvolatile circuitry to store the address of the defective memory element that the redundant element is to logically replace. Additionally each redundant element may have a nonvolatile programmable enable bit to enable the redundant element to replace the defective element if the address of the defective element is detected. The nonvolatile address and enable storage is typically made up of laser fuse or electrical antifuse elements—generically called fuses. For laser fuses, lines are drawn in a material such that they can be cut open with a laser to change the state of the fuse from a short circuit or low impedance to an open circuit or high impedance. An antifuse may be comprised of a capacitor which is a high impedance or open circuit that can be blown when a high voltage is applied across the capacitor plates. When the antifuse is blown, the capacitor plates are shorted out, and the device has a short circuit or low impedance characteristic. Typically a signal is applied to the fuse element, and the low impedance or high impedance state is detected and stored in a latch. The output of the latch for the enable fuse is used as the enable signal for the associated redundant row or column array element.
In FIGS. 2A and 2B, a fuse bank array is shown having a set of row fuse banks (30A-30D, 33A-33D) and a set of column fuse banks (31A-31D, 34A-34D). The fuse bank array may be part of the fuse banks 25 on the memory chip 12 in FIG. 1. Thus, there are four row fuse banks (30A-30D, 33A-33D) in the fuse bank arrays in FIGS. 2A-2B to correspond to the four redundant rows RR0-RR3, and there are four column fuse banks (31A-31D, 34A-34D) associated with the four redundant columns RC0-RC3. The row and column fuse banks are used to store memory addresses of respective non-redundant rows/columns that are found to be defective. Based on the match between the address stored in a fuse bank and the address presented on the address bus 17, an associated redundant memory location may be selected to store data in place of the non-redundant location specified in the address on the bus 17. Thus, the redundant memory elements (rows and columns) may not actually have corresponding address lines to decode them (contrary to the address lines for the non-redundant memory elements) so as to directly access the redundant rows. Instead, the redundant elements may be directly wired to corresponding fuse banks and selected/activated using the status (blown or unblown) of fuses in the corresponding fuse banks. That is, the address presented on the address bus 17 may always refer to a memory element in the non-redundant memory array 30 and there may not be a separate “redundant memory address” in the system.
In the discussion herein, the term “fuse bank” refers to a set of address fuses and one enable fuse associated therewith—the fuse elements—in the memory chip 12 as discussed later hereinbelow with reference to FIG. 4. Thus, as noted before, when the (row/column) address stored in the fuse bank matches with the memory address presented (e.g., on the address bus 17), then the redundant element associated with that bank of fuses is activated. It is thus observed that the combination of all of the values of the fuse elements (blown or unblown) in a fuse bank constitutes a memory address that is to be repaired. That is, the redundant memory element (row or column) associated with that fuse bank is to be used instead of the non-redundant or “regular” memory element at that address (i.e., the memory element whose address was provided on the address bus 17).
FIG. 3 shows a high level block diagram of an exemplary memory address path in the memory chip 12 in FIG. 1. As is known, a memory “address” is typically a multiplexed address input that is used to present (through the address bus 17) a row address and then a column address to the memory device 12. A memory “address” may be 14 bits of address information and may have different numbers of active bits for row addresses versus column addresses. The externally-received memory address (constituting row address and column address portions) is shown presented at the address line/bus 17 in FIG. 3. For the sake of simplicity, only one address line 17 is shown in FIG. 3 instead of a group of address lines constituting the address bus 17. As noted before, the address on line 17 is for a memory element in a non-redundant memory array (e.g., the memory array of R0-R7:C0-C7 in FIGS. 2A-2B). The row address portion is latched in the row latch/counter 36. The row address counter 36 provides the row address for Auto Refresh or for Self Refresh modes. The column address is latched in the column latch/counter 38. The column address counter 38 provides subsequent column addresses within a burst read or write data access. The row and column addresses are also presented to the row and column redundancy comparators 40, 42, respectively, to determine if the current address (on line 17) is a match to a previously detected failing address. If a row address matches an address stored in the row fuse banks (shown, for example, in FIG. 2A) and the associated row fuse bank enable is true (as indicated by the blown status of the corresponding enable fuse), then a redundant row address is to be used in place of the normal row address. Likewise for the column address.
In FIG. 3, the block labeled Row Fuses 44 will typically contain many banks of row address fuses each with a corresponding enable fuse. Likewise for the block Column Fuses 46. The row and column address are also presented to the row and column address decoders 48, 50, respectively. The decoders are used to decode the address (of the non-redundant memory element) to activate the corresponding row line or column select line to access the addressed memory cell in the set of memory cells 20. If a redundant match occurs (as indicated by the outputs of the comparators 40 and 42), typically the normal (non-redundant) memory element will be disabled. That is, the normal row line will not be activated if a redundant row line is activated. Hence, the match signals from comparators 40, 42 are used as enable signals for the redundant element drivers 52, 54 and as a disable for the normal decoders 48, 50. However, some memory devices may choose to activate both a redundant element and a normal element and use the match signal to determine which data lines to/from the array contain valid information. As noted before, the memory cells 20 may contain non-redundant and redundant memory elements. Thus, in the embodiment of FIG. 3, the memory cell array 20 receives the row and column signals and enables access to the associated memory element (redundant or non-redundant). The output from the selected memory cell(s) is supplied to the data line/data bus 18 via data sense amplifiers 56 as is known in the art. It is noted here that for the sake of simplicity, only one data line 18 is shown in FIG. 3 instead of a set of data lines constituting the data bus 18.
FIG. 4 is a block level diagram of a fuse bank 58. The fuse bank 58 may be one of the fuse banks in the row and column fuse banks shown in FIGS. 2A-2B. In the example of FIG. 4, eight fuses 59A-59H are provided to store an address (row or column address) of a non-redundant memory element to be repaired. An additional fuse 59I is provided as an enable fuse for the fuse bank 58. Each fuse element 59A-59I has an associated fuse latch 60A-60I, respectively, to store the state of the fuse therein (i.e., the address information stored in the corresponding fuse element and the enable status). The fuses 59A-59I may be read (and, hence, their outputs latched) periodically upon refresh or at some other predetermined intervals. The outputs of all fuse latches 60A-60I may then be provided to respective memory address comparator circuits (e.g., comparators 40 and 42 in FIG. 3). It is not necessarily required that every non-redundant memory address bit have an associated fuse. That is, in case of an 8-bit address in FIG. 4, there may be less than eight fuse elements in the fuse bank 58. Some address bits may be used to determine which fuse banks are to be used, or a single fuse bank may match multiple addresses. This allows for a single fuse bank to have a larger repair region on the device, where the other non-compared address bits are used in combination with the match signal (e.g., a signal generated by the row comparator 40 or the column comparator 42 in FIG. 3) to select the appropriate redundant element to activate. In any event, the enable fuse element 59I still remains present as part of the fuse bank 58.
FIG. 5 is a high level diagram of a comparator circuit 62 that may be part of the row comparators 40 or the column comparators 42 in FIG. 3. The repair address (e.g., the address output from the fuse latches 60A-60H in FIG. 4) and the address on line 17 are compared by exclusive NORing each of the corresponding bits together. If the bits are the same, the output of the XNOR is high. If all XNOR outputs for a given fuse bank are “high”, then all address bits match. All XNOR outputs are ANDed together to form the first address match signal (the Address_Match signal in FIG. 5). The enable signal from the enable fuse latch 60I is ANDed with the Address_Match signal to form the “Match” signal, which may be output as the Row_Match signal or the Column_Match signal (depending on whether row or column addresses are being compared) indicated in FIG. 3. Different logic methods of performing this compare function are well known in the art.
All fuses in the fuse banks 25 on the memory chip 12 are typically read shortly after power is applied to the chip 12. The fuse status or address information read from the fuse elements is stored in corresponding latches. The output of the latches will be all low or all high for unprogrammed fuses depending on the fuse technology (there will be a default unprogrammed state for a laser fuse or an electrical antifuse element). If this default state is all low, for example, then this unprogrammed address would match an applied address of all zeros. To differentiate between an unprogrammed fuse bank, and one intended to replace a defective non-redundant memory element at address zero, the enable fuse is required. If the enable fuse is blown, and the fuse address matches with the externally-supplied address on line 17, then the redundant element associated with that fuse bank is used. Likewise if the default or unprogrammed state is all ones, then the enable fuse is used to differentiate between an address of all ones and an unblown set of addresses in a fuse bank.
In operation, the defective address information stored in fuses is read and stored in latches after power is applied to the device 12. When a row address is applied to the device 12 (on the address bus 17), any redundant row that may be used to replace the row being addressed has its stored fuse address compared to the row address to see if it is a match. If it does match, and if the associated enable fuse is also blown, then the normal (non-redundant) row is not turned on, but rather the redundant row is used. It is possible to have a design where both the redundant and normal row turn on, but data associated with the redundant one is selected for use. Typically, the selection/activation of normal row or column is slightly delayed because the address compare circuitry (e.g., the comparators 40, 42 in FIG. 3) needs some time to perform the address comparison and generate a match signal which is used to turn on the redundant element and prevent the normal element from turning on.